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A BIST architecture for testing LUTs in a Virtex-4 FPGA
Contents
Abstract
Acknowledgements
Table of Contents
List of Tables
List of Figures
1 Introduction
1.1 Field Programmable Gate Arrays
1.2 Built in Self-Test (BIST)
1.3 Advantages of BIST
1.4 Disadvantages of BIST
1.5 Literature Survey
1.6 Organization of Thesis
2 Fault Types and Algorithms
2.1 Introduction
2.2 SRAM Cell
2.3 Functional Model
2.4 Electrical Structure for SRAMs
2.5 SRAM Read and Write Circuitries
2.6 Faults
2.6.1 SRAM Memory Faults
2.7 Analysis of Faults in SRAM Cell
2.8 Advanced Memory Test
2.9 MATS and MATS+ Algorithms
2.10 MARCH C-Algorithm
2.11 Extended MarchC- Algorithm
2.12 March Tests
2.13 Selection of the Testing Algorithm
3 SRAM Based FPGA
3.1 Introduction
3.2 Anatomy of the FPGA
3.3 Benefits and Drawbacks of FPGAs
3.4 FPGA Applications
3.5 FPGA Device Manufactures
3.6 SRAM Programmable Virtex-4 FPGA
3.6.1 I/O Blocks
3.6.2 Block RAM Modules (BRAMs)
3.6.3 Cascadable Embedded Xtreme DSPSlices
3.6.4 Digital Clock Managers (DCMs)
3.6.5 Configurable Logic Block (CLBs)
3.7 Need for Testing FPGAs
4 Proposed Architecture for Testing Look up Tables in a Virtex-4 FPGA
4.1 Test Pattern Generator (TPG)
4.2 Circuit Under Test (CUT) and Output Response Analyzer (ORA)
4.3 BISTArchitecture
4.4 Fault Modeling and Detection using Extended MarchC- Algorithm
4.5 Pseudo Code
4.6 Fault Modeling and Detection
4.6.1 Stuck-at Fault
4.6.2 Transition Fault
4.6.3 Address Decoder Fault
4.6.4 Incorrect Read Fault
4.6.5 Read Destructive Fault
4.6.6 Deceptive Read Destructive Fault
4.6.7 Data Retention Fault
4.6.8 Coupling Faults
5 Simulation Results and Performance Analysis
5.1 Introduction
5.2 Simulation Results
5.3 Simulations without Faults
5.4 Stuck-at 1 Fault
5.5 Stuck-at 0 Fault
5.6 Up-Transient Fault
5.7 Down-Transient Fault
5.8 Address Decoder Fault
5.9 Incorrect Read Fault
5.10 Read Destructive Fault
5.11 Deceptive Read Destructive Fault
5.12 Data Retention Fault
5.13 State Coupling Fault
5.14 Up-Transient Coupling Fault
5.15 Down-Transient Coupling Fault
5.16 Incorrect Read Coupling Fault
5.17 Read Destructive Coupling Fault
5.18 Deceptive Read Destructive Coupling Fault
5.19 Analysis of Results
6 Conclusion
6.1 Contributions
6.2 Future work
References Bài viết liên quan
